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Table 4-1 · General Parameters (Continued)
Name
INTERRUPT_MODE
ENABLE_FIFOSTAT
USE_REGISTERS
MADDR_WIDTH
GENERATE_PCICLK
USE_GLOBAL_CLK
USE_GLOBAL_RESET
USE_GLOBAL_TRDY
USE_GLOBAL_IRDY
ONCHIP_ARBITER
36
Values
0 to 2
0 to 1
0 or 1
8 to 32
0 or 1
0, 1, or 2
0 or 1
0 or 1
0 or 1
0 or 1
Description
Configures the PCI interrupt:
0: The interrupt register is implemented as per Table 7-15 on page 111 and Table 7-21 on
page 113 .
1: The interrupt system is disabled.
2: The interrupt register (48h) is not implemented, and the EXT_INTn input directly drives
INTAn.
When Master functions are enabled (MASTER = 1), this parameter should be set to 0.
When INTERRUPT_MODE is set to 0 or 2, the interrupt disable and status bits in the
configuration space control and status registers are implemented and may be used to disable the
interrupt.
When 1, the FIFO status register as per Table 7-16 on page 112 is implemented.
When 1, the internal RAM blocks are replaced with a register-based implementation.
For SX-A and RTSX-S, the internal RAM blocks are always replaced with registers.
Specifies the width of the backend address bus. This should match the largest BAR address
width ( Table 4-3 on page 38 ). For example, if 64 kB of address space are configured,
MADDR_WIDTH should be set to 16. If all BARs are less than 256 bytes,
MADDR_WIDTH should be set to 8. Values below 8 are not permitted.
Memory Size = 2 MADDR_WIDTH
Set to 1 when the core is required to generate the PCI clock.
Controls the sort of clock buffer used.
0: No buffer is used. The synthesis tool will insert a buffer.
1: A standard clock buffer is used.
2: When using AX/RTAX-S families, uses a CLKBUF instead of a HCLKBUF cell
Actel recommends setting this parameter to 1.
When 1, a global buffer is used to drive the internal reset network in the core. When 0, normal
routing resources are used, and due to the high fanout of the reset network, a buffer tree will be
created for it. Actel recommends that this parameter be set to 1.
When 1 and MASTER = 1, a global buffer is used to drive the internal TRDY network in the
core. When 0, normal routing resources are used. Actel recommends that this parameter be set
to 1.
When 1 and TARGET = 1, a global buffer is used to drive the internal IRDY network in the
core. When 0, normal routing resources are used. Actel recommends that this parameter be set
to 1.
In some applications, the FPGA will be the system controller as well, and include the PCI
arbiter. When 1, this removes the pads from the REQN and GNTN I/Os, allowing
connection inside the FPGA and enabling the FRAMEN_OUT and IRDYN_OUT outputs.
v4.0
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